ST STM32L4+ Series Reference Manual page 113

RM0432
3 Embedded Flash memory (FLASH)
3.1 Introduction
The Flash memory interface manages CPU AHB ICode and DCode accesses to the Flash
memory. It implements the erase and program Flash memory operations and the read and
write protection mechanisms.
The Flash memory interface accelerates code execution with a system of instruction
prefetch and cache lines.
3.2 FLASH main features
•
Up to 2 Mbytes of Flash memory with dual-bank architecture supporting read-while-
write capability (RWW).
•
Flash memory read operations with two data width modes supported:
–
–
•
Page erase, bank erase and mass erase (both banks)
Flash memory interface features:
•
Flash memory read operations
• Flash memory program/erase operations
•
Read protection activated by option (RDP)
• 4 Write protection areas (2 per bank when DBANK=1 and 4 for full memory when
DBANK=0)
•
2 proprietary code read protection areas (1 per bank when DBANK=1, 2 for all memory
when DBANK=0)
•
Flash empty check
•
Prefetch on ICODE
•
Instruction Cache: 32 cache lines of 4 x 64 or 2 x 128 bits on ICode (1 Kbyte RAM)
•
Data Cache: 8 cache lines of 4 x 64 bits or 2 x 128 on DCode (256 bytes RAM)
•
Error Code Correction ECC: 8 bits per 64-bit double-word
–
–
•
Option byte loader
•
Low-power mode
Single-bank mode DBANK=0: read access of 128 bits
Dual-bank mode DBANK=1: read access of 64 bits
DBANK=1: 8 + 64 = 72 bits, 2 bits detection, 1 bit correction
DBANK=0: (8+64) + (8+64) = 144 bits, 2 bits detection, 1 bit correction
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Embedded Flash memory (FLASH)
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