ST STM32L4+ Series Reference Manual page 724

Analog-to-digital converters (ADC)
Table 142. ADC register map and reset values for each ADC (offset=0x000
Offset Register
ADC_DIFSEL
0xB0
Reset value
ADC_CALFACT
0xB4
Reset value
Table 143. ADC register map and reset values (master and slave ADC
Offset Register
ADC_CSR
0x00
Reset value
0x04 Reserved
ADC_CCR
0x08
Reset value
ADC_CDR
0x0C
Reset value 0
Refer to
724/2301
for master ADC, 0x100 for slave ADC) (continued)
common registers) offset = 0x300
0 0 0 0
0 0
RDATA_SLV[15:0]
0 0 0 0 0 0 0 0
Section 2.2 on page 91
0 0 0 0
CALFACT_D[6:0]
0 0 0 0 0 0 0
slave ADC2
0 0 0 0 0 0 0
Res.
PRESC[3:0]
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
for the register boundary addresses.
RM0432 Rev 6
DIFSEL[18:0]
0 0 0 0 0 0 0 0 0
0
master ADC1
0 0 0 0 0
DELAY[3:0]
0 0 0 0 0 0
RDATA_MST[15:0]
0 0 0 0 0 0 0 0 0
RM0432
0 0 0 0 0 0
CALFACT_S[6:0]
0 0 0 0 0 0
0 0 0 0 0 0
DUAL[4:0]
0 0 0 0 0
0 0 0 0 0 0