ST STM32L4+ Series Reference Manual page 262

Reset and clock control (RCC)
Access: 0 ≤ wait state ≤ 2, word, half-word and byte access
1 or 2 wait states inserted only if the access occurs during clock source switch.
From 0 to 15 wait states inserted if the access occurs when the APB or AHB prescalers
values update is on going.
31 30 29
Res. MCOPRE[2:0]
rw rw
15 14 13
STOP
Res. PPRE2[2:0]
WUCK
rw rw
Bit 31 Reserved, must be kept at reset value.
Bits 30:28 MCOPRE[2:0]: Microcontroller clock output prescaler
Bits 27:24 MCOSEL[3:0]: Microcontroller clock output
Note: This clock output may have some truncated cycles at startup or during MCO clock
Bits 23:16 Reserved, must be kept at reset value.
STOPWUCK: Wakeup from Stop and CSS backup clock selection
Bit 15
Bit 14 Reserved, must be kept at reset value.
262/2301
28 27 26 25
MCOSEL[3:0]
rw rw rw rw
12 11 10 9
PPRE1[2:0]
rw rw rw rw
These bits are set and cleared by software.
It is highly recommended to change this prescaler before MCO output is enabled.
000: MCO is divided by 1
001: MCO is divided by 2
010: MCO is divided by 4
011: MCO is divided by 8
100: MCO is divided by 16
Others: not allowed
Set and cleared by software.
0000: MCO output disabled, no clock on MCO
0001: SYSCLK system clock selected
0010: MSI clock selected.
0011: HSI16 clock selected.
0100: HSE clock selected
0101: Main PLL clock selected
0110: LSI clock selected
0111: LSE clock selected
1000: Internal HSI48 clock selected
Others: Reserved
source switching.
Set and cleared by software to select the system clock used when exiting Stop mode.
The selected clock is also used as emergency clock for the Clock Security System on HSE.
Warning: STOPWUCK must not be modified when the Clock Security System is enabled by
HSECSSON in RCC_CR register and the system clock is HSE (SWS="10") or a switch on
HSE is requested (SW="10").
0: MSI oscillator selected as wakeup from stop clock and CSS backup clock.
1: HSI16 oscillator selected as wakeup from stop clock and CSS backup clock
24 23 22
Res. Res.
rw
8 7 6
HPRE[3:0]
rw rw rw
RM0432 Rev 6
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
SWS[1:0]
rw rw r r
RM0432
17 16
Res. Res.
1 0
SW[1:0]
rw rw