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RM0432
Bits 31:16 CXPOS[15:0]: current X position
These bits return the current X position.
Bits 15:0 CYPOS[15:0]: current Y position
These bits return the current Y position.
29.8.13
LTDC current display status register (LTDC_CDSR)
This register returns the status of the current display phase which is controlled by the
HSYNC, VSYNC, and horizontal/vertical DE signals.
Example: if the current display phase is the vertical synchronization, the VSYNCS bit is set
(active high). If the current display phase is the horizontal synchronization, the HSYNCS bit
is active high.
Address offset: 0x48
Reset value: 0x0000 000F
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:4 Reserved, must be kept at reset value.
Bit 3 HSYNCS: horizontal synchronization display status
0: active low
1: active high
Bit 2 VSYNCS: vertical synchronization display status
0: active low
1: active high
Bit 1 HDES: horizontal data enable display status
0: active low
1: active high
Bit 0 VDES: vertical data enable display status
0: active low
1: active high
Note:
The returned status does not depend on the configured polarity in the LTDC_GCR register,
instead it returns the current active display phase.
29.8.14
LTDC layer x control register (LTDC_LxCR)
Address offset: 0x84 + 0x80 * (x - 1), (x = 1 to 2)
Reset value: 0x0000 0000
27
26
25
24
Res.
Res.
Res.
Res.
11
10
9
8
Res.
Res.
Res.
Res.
RM0432 Rev 6
LCD-TFT display controller (LTDC)
23
22
21
20
Res.
Res.
Res.
Res.
7
6
5
4
Res.
Res.
Res.
Res.
19
18
17
Res.
Res.
Res.
3
2
1
HSYNCS VSYNCS
HDES
r
r
r
911/2301
16
Res.
0
VDES
r
923
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