ST STM32L4+ Series Reference Manual page 569

RM0432
Write operation with no latency
Some devices can also require a zero latency for the write operations.
This zero write latency can be forced by setting the write zero latency (WZL) bit of
OCTOSPI_HLCR).
CS#
CK
RWDS
DQ[7:0]
Latency on page-crossing during the read operations
An additional latency can be needed by some devices for the read operation when crossing
pages.
The initial latency must be respected for any page access, as a consequence, when the first
access is close to the page boundary, a latency is automatically added at the page crossing
to respect the t
CS#
CK
RDS
DQ[7:0]
19.4.6 Common functionality between the Regular-command and
HyperBus modes
The OCTOSPI supports some specific features common to both the Regular-command and
the HyperBus modes, such as:
•
CS boundary and regulation
CS boundary and refresh
Two processes can be activated to regulate the OCTOSPI transactions:
•
CS boundary
•
Refresh
Figure 80. HyperBus write operation with no latency
Memory drives RWDS but master ignores
39:32
47:40
time.
ACC
Figure 81. HyperBus read operation page crossing with latency
12 Clock
Initial Latency
A0 02 46 8A 80 07
Read from Address = 123457h
RM0432 Rev 6
23:16
31:24 15:8
Command-Address
9 Words
Data
dd dd dd dd dd dd dd dd dd dd
Address Address
Address Address
12345D 12345E
123457 123458
Octo-SPI interface (OCTOSPI)
7:0 15:8 7:0
Data
3 Clock Initial Page
Crossing Latency
dd dd dd dd
Address Address Address
12345F 123460
MSv43497V1
123461
MSv43498V1
569/2301
603