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LCD-TFT display controller (LTDC)
29.8.25
LTDC layer x CLUT write register (LTDC_LxCLUTWR)
This register defines the CLUT address and the RGB value.
Address offset: 0xC4 + 0x80 * (x - 1), (x = 1 to 2)
Reset value: 0x0000 0000
31
30
29
28
CLUTADD[7:0]
w
w
w
w
15
14
13
12
GREEN[7:0]
w
w
w
w
Bits 31:24 CLUTADD[7:0]: CLUT address
These bits configure the CLUT address (color position within the CLUT) of each RGB value.
Bits 23:16 RED[7:0]: red value
These bits configure the red value.
Bits 15:8 GREEN[7:0]: green value
These bits configure the green value.
Bits 7:0 BLUE[7:0]: blue value
These bits configure the blue value.
Note:
The CLUT write register must be configured only during blanking period or if the layer is
disabled. The CLUT can be enabled or disabled in the LTDC_LxCR register.
The CLUT is only meaningful for L8, AL44 and AL88 pixel format.
920/2301
27
26
25
24
w
w
w
w
11
10
9
8
w
w
w
w
RM0432 Rev 6
23
22
21
20
RED[7:0]
w
w
w
w
7
6
5
4
BLUE[7:0]
w
w
w
w
RM0432
19
18
17
16
w
w
w
w
3
2
1
0
w
w
w
w
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