ST STM32L4+ Series Reference Manual page 699

RM0432
Bits 19:17 DISCNUM[2:0]: Discontinuous mode channel count
These bits are written by software to define the number of regular channels to be converted in
discontinuous mode, after receiving an external trigger.
000: 1 channel
001: 2 channels
...
111: 8 channels
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no
regular conversion is ongoing).
When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bits
DISCNUM[2:0] of the slave ADC are no more writable and their content is equal to the bits
DISCNUM[2:0] of the master ADC.
Bit 16 DISCEN: Discontinuous mode for regular channels
This bit is set and cleared by software to enable/disable Discontinuous mode for regular channels.
0: Discontinuous mode for regular channels disabled
1: Discontinuous mode for regular channels enabled
Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden
to set both DISCEN=1 and CONT=1.
It is not possible to use both auto-injected mode and discontinuous mode simultaneously: the
bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set.
The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular
conversion is ongoing).
When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bit
DISCEN of the slave ADC is no more writable and its content is equal to the bit DISCEN of the
master ADC.
Bit 15 Reserved, must be kept at reset value.
Bit 14 AUTDLY: Delayed conversion mode
This bit is set and cleared by software to enable/disable the Auto Delayed Conversion mode.
0: Auto-delayed conversion mode off
1: Auto-delayed conversion mode on
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bit
AUTDLY of the slave ADC is no more writable and its content is equal to the bit AUTDLY of the
master ADC.
Bit 13 CONT: Single / continuous conversion mode for regular conversions
This bit is set and cleared by software. If it is set, regular conversion takes place continuously until it
is cleared.
0: Single conversion mode
1: Continuous conversion mode
Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden
to set both DISCEN=1 and CONT=1.
The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular
conversion is ongoing).
When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bit
CONT of the slave ADC is no more writable and its content is equal to the bit CONT of the
master ADC.
RM0432 Rev 6
Analog-to-digital converters (ADC)
699/2301
724