ST STM32L4+ Series Reference Manual page 514

Flexible static memory controller (FSMC)
Bit number
31:24
23:22
21
20
19
18:16
15
14
13
12
11
10
9
8
7
6
5:4
3:2
1
0
Bit number
31:30
29:28
27:24
23:20
19:16
15:8
7:4
3:0
514/2301
Table 98. FMC_BCRx bitfields (mode 2/B)
Bit name
Reserved 0x000
NBLSET[1:0] Don't care
WFDIS As needed
CCLKEN As needed
CBURSTRW 0x0 (no effect in Asynchronous mode)
CPSIZE 0x0 (no effect in Asynchronous mode)
ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0.
EXTMOD 0x1 for mode B, 0x0 for mode 2
WAITEN 0x0 (no effect in Asynchronous mode)
WREN As needed
WAITCFG Don't care
Reserved 0x0
WAITPOL Meaningful only if bit 15 is 1
BURSTEN 0x0
Reserved 0x1
FACCEN 0x1
MWID As needed
MTYP 0x2 (NOR Flash memory)
MUXEN 0x0
MBKEN 0x1
Table 99. FMC_BTRx bitfields (mode 2/B)
Bit name
Duration of the data hold phase (DATAHLD HCLK cycles for read
DATAHLD accesses and DATAHLD+1 HCLK cycles for write accesses when
Extended mode is disabled).
ACCMOD 0x1 if Extended mode is set
DATLAT Don't care
CLKDIV Don't care
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
Duration of the access second phase (DATAST HCLK cycles) for
DATAST
read accesses.
ADDHLD Don't care
Duration of the access first phase (ADDSET HCLK cycles) for read
ADDSET
accesses. Minimum value for ADDSET is 0.
RM0432 Rev 6
Value to set
Value to set
RM0432