ST STM32L4+ Series Reference Manual page 410

DMA request multiplexer (DMAMUX)
12.6 DMAMUX registers
Refer to the table containing register boundary addresses for the DMAMUX base address.
DMAMUX registers may be accessed per (8-bit) byte, (16-bit) half-word, or (32-bit) word.
The address must be aligned with the data size.
12.6.1 DMAMUX request line multiplexer channel x configuration register
(DMAMUX_CxCR)
Address offset: 0x000 + 0x04 * x (x = 0 to 13)
Reset value: 0x0000 0000
31 30 29
Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:29 Reserved, must be kept at reset value.
Bits 28:24 SYNC_ID[4:0]: Synchronization identification
Selects the synchronization input (see
inputs to resources (STM32L4Rxxx and STM32L4Sxxx devices)
assignment of synchronization inputs to resources (STM32L4P5xx and STM32L4Q5xx
devices)).
Bits 23:19 NBREQ[4:0]: Number of DMA requests minus 1 to forward
Defines the number of DMA requests to forward to the DMA controller after a synchronization
event, and/or the number of DMA requests before an output event is generated.
This field shall only be written when both SE and EGE bits are low.
Bits 18:17 SPOL[1:0]: Synchronization polarity
Defines the edge polarity of the selected synchronization input:
00: no event, i.e. no synchronization nor detection.
01: rising edge
10: falling edge
11: rising and falling edge
Bit 16 SE: Synchronization enable
0: synchronization disabled
1: synchronization enabled
Bits 15:10 Reserved, must be kept at reset value.
Bit 9 EGE: Event generation enable
0: event generation disabled
1: event generation enabled
Bit 8 SOIE: Synchronization overrun interrupt enable
0: interrupt disabled
1: interrupt enabled
410/2301
28 27 26 25
SYNC_ID[4:0]
rw rw rw rw
12 11 10 9
Res. Res. EGE
rw
24 23 22
NBREQ[4:0]
rw rw rw
8 7 6
SOIE Res.
rw rw
Table 58: DMAMUX: assignment of synchronization
RM0432 Rev 6
21 20 19 18
SPOL[1:0]
rw rw rw rw
5 4 3 2
DMAREQ_ID[6:0]
rw rw rw rw
and Table 59: DMAMUX:
RM0432
17 16
SE
rw rw
1 0
rw rw