ST STM32L4+ Series Reference Manual page 455

RM0432
192/256 x 16-byte blocks per line
Physical buffer
Line N first block on
Virtual buffer overview
For a frame buffer coded in 32bpp or 16bpp, the virtual buffer can be configured to have 192
or 256 blocks. This will result in a virtual frame buffer of 768 x 1024 or 1024 x 1024 pixels for
32bpp and 1536 x 1024 or 2048 x 1024 for 16bpp.
For a frame buffer coded in 24bpp, the virtual buffer shall be configured to have 192 blocks
to have an integer number of pixel per lines. This will result in a virtual frame buffer of
1024 x 1024 pixels for 24bpp.
Each buffer can be physically mapped anywhere in the physical memory thanks to:
•
The physical buffer base address (PBBA) field of the graphic MMU buffer x
configuration register (GFXMMU_BxCR). It configures the physical location of the
8 MByte area where the buffer is mapped.
•
The physical buffer location respective to the physical buffer base address is defined by
the physical buffer offset (PBO) field of the graphic MMU buffer x configuration register
(GFXMMU_BxCR).
16-byte block
Line N first block on screen
Virtual buffer
Configuration
1024 lines
Line N last block
screen on screen
Figure 39. Virtual buffer
192/256 blocks (3072/4096 Byte)
Continuous memory locations
Line N+1 first
block on screen
RM0432 Rev 6
Chrom-GRC™ (GFXMMU)
Out screen block
Line N+1 last
block on screen
Line N+1 last
block on screen
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