ST STM32L4+ Series Reference Manual page 213

RM0432
SRAM2 content is preserved). The PLL, the HSI16, the MSI and the HSE oscillators are
also switched off.
SRAM1 and register contents are lost except for registers in the Backup domain and
Standby circuitry (see
and STM32L4Q5xx) or fully preserved depending on RRS[1:0] bits configuration in
PWR_CR3 register. In this case the Low-power regulator is ON and provides the supply to
SRAM2 only.
The BOR is always available in Standby mode. The consumption is increased when
thresholds higher than V
I/O states in Standby mode
In the Standby mode, the IO's are by default in floating state. If the APC bit of PWR_CR3
register has been set, the I/Os can be configured either with a pull-up (refer to
PWR_PUCRx registers (x=A,B,C,D,E,F,G,H)), or with a pull-down (refer to PWR_PDCRx
registers (x=A,B,C,D,E,F,G,H)), or can be kept in analog state if none of the PWR_PUCRx
or PWR_PDCRx register has been set. The pull-down configuration has highest priority over
pull-up configuration in case both PWR_PUCRx and PWR_PDCRx are set for the same IO.
Some I/Os (listed in
debug and can only be configured to their respective reset pull-up or pull-down state during
Standby mode setting their respective bit in the PWR_PUCRx or PWR_PDCRx registers to
'1', or will be configured to floating state if the bit is kept at '0'.
The RTC outputs on PC13 are functional in Standby mode. PC14 and PC15 used for LSE
are also functional. 5 wakeup pins (WKUPx, x=1,2...5) and the 3 RTC tampers are available.
Entering Standby mode
The Standby mode is entered according
SLEEPDEEP bit in the Cortex
Refer to
In Standby mode, the following features can be selected by programming individual control
bits:
•
Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started it cannot be stopped except by a reset. See
Section 44.3: IWDG functional description
(IWDG).
• real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain
control register (RCC_BDCR)
•
Internal RC oscillator (LSI): this is configured by the LSION bit in the Control/status
register (RCC_CSR).
•
External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the Backup
domain control register (RCC_BDCR)
Exiting Standby mode
The Standby mode is exited according
flag in the
mode. All registers are reset after wakeup from Standby except for
(PWR_CR3).
Figure 9). SRAM2 content can be partially (only for STM32L4P5xx
are used.
BOR0
Section 8.3.1: General-purpose I/O
®
Table 34: Standby mode
Power control register 3 (PWR_CR3)
Section : Entering low-power
-M4 System Control register is set.
for details on how to enter Standby mode.
in Section 44: Independent watchdog
Section : Entering low-power
indicates that the MCU was in Standby
RM0432 Rev 6
Power control (PWR)
(GPIO)) are used for JTAG/SW
mode, when the
mode. The SBF status
Power control register 3
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