ST STM32L4+ Series Reference Manual page 748

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Digital-to-analog converter (DAC)

Bits 5:2 TSEL1[3:0]: DAC channel1 trigger selection

These bits select the external event used to trigger DAC channel1

0000: SWTRIG1

0001: dac_ch1_trig1

0010: dac_ch1_trig2

1111: dac_ch1_trig15

Refer to the trigger selection tables in

trigger configuration and mapping.

Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled).

Bit 1 TEN1: DAC channel1 trigger enable

This bit is set and cleared by software to enable/disable DAC channel1 trigger.

0: DAC channel1 trigger disabled and data written into the DAC_DHR1 register are

transferred one APB1 clock cycle later to the DAC_DOR1 register

1: DAC channel1 trigger enabled and data from the DAC_DHR1 register are transferred

three APB1 clock cycles later to the DAC_DOR1 register

Note: When software trigger is selected, the transfer from the DAC_DHR1 register to the

Bit 0 EN1: DAC channel1 enable

This bit is set and cleared by software to enable/disable DAC channel1.

0: DAC channel1 disabled

1: DAC channel1 enabled

DAC software trigger register (DAC_SWTRGR)

Address offset: 0x04

Reset value: 0x0000 0000

DAC_DOR1 register takes only one APB1 clock cycle.

RM0432 Rev 6

Section 22.4.6: DAC trigger selection

for details on

SWTRIG2 SWTRIG1

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