ST STM32L4+ Series Reference Manual page 884

Digital filter for sigma delta modulators (DFSDM)
Table 191. DFSDM register map and reset values (continued)
Register
Offset
name
DFSDM_
CH7CFGR1
0xE0
reset value
DFSDM_
CH7CFGR2
0xE4
reset value 0
DFSDM_
CH7AWSCDR
0xE8
reset value
DFSDM_
CH7WDATR
0xEC
reset value
DFSDM_
CH7DATINR
0xF0
reset value 0
DFSDM_
CH7DLYR
0xF4
reset value
0xF8 -
Reserved
0xFC
DFSDM_
FLT0CR1
0x100
reset value
DFSDM_
FLT0CR2
0x104
reset value
DFSDM_
FLT0ISR
0x108
reset value 0
DFSDM_
FLT0ICR
0x10C
reset value 0
DFSDM_
FLT0JCHGR
0x110
reset value
DFSDM_
FLT0FCR
0x114
reset value 0
884/2301
0 0 0 0 0 0 0 0 0
0 0
INDAT1[15:0]
0 0 0 0 0 0 0 0 0
RCH[2:0]
0 0 0 0 0
0 0
SCDF[7:0]
0 0 0 0 0 0 0 1 1
CLRSCDF[7:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0
0 0
OFFSET[23:0]
0 0 0 0 0 0 0 0
AWFOSR[4:0] BKSCD[3:0]
0 0 0 0 0 0 0
0 0
0 0 0 0 0 0 0 0
0 0 0 0 0
AWDCH[7:0]
0 0 0 0 0 0 0 0
CKABF[7:0]
1 1 1 1 1 1 0
CLRCKABF[7:0]
0 0 0 0 0 0
FOSR[9:0]
0 0 0 0 0 0
RM0432 Rev 6
0 0 0 0 0 0
DTRBS[4:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0
WDATA[15:0]
0 0 0 0 0 0 0 0 0
INDAT0[15:0]
0 0 0 0 0 0 0 0 0
0
JEXTSEL[4:0]
0 0 0 0 0 0 0
EXCH[7:0]
0 0 0 0 0 0 0 0
0
0 0 0
0 0 0
RM0432
0 0 0 0
0 0
SCDT[7:0]
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
PLSSKP[5:0]
0 0 0 0 0
0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0
JCHG[7:0]
0 0 0 0 1
IOSR[7:0]
0 0 0 0 0