ST STM32L4+ Series Reference Manual page 515

RM0432
Bit number
31:30
29:28
27:24
23:20
19:16
15:8
7:4
3:0
Note: The FMC_BWTRx register is valid only if the Extended mode is set (mode B), otherwise its
content is don't care.
Mode C - NOR Flash - OE toggling
A[25:0]
NADV
NEx
NOE
NWE
D[15:0]
Table 100. FMC_BWTRx bitfields (mode 2/B)
Bit name
Duration of the data hold phase (DATAHLD+1 HCLK cycles for write
DATAHLD
accesses).
ACCMOD 0x1 if Extended mode is set
DATLAT Don't care
CLKDIV Don't care
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
Duration of the access second phase (DATAST HCLK cycles) for
DATAST
write accesses.
ADDHLD Don't care
Duration of the access first phase (ADDSET HCLK cycles) for write
ADDSET
accesses. Minimum value for ADDSET is 0.
Figure 55. Mode C read access waveforms
High
ADDSET HCLK cycles
RM0432 Rev 6
Flexible static memory controller (FSMC)
Value to set
Memory transaction
Data driven by memory
DATAST HCLK cycles DATAHLD
HCLK cycles
MSv41682V1
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