ST STM32L4+ Series Reference Manual page 811

RM0432
Interrupt event Event flag
COMP1 output
COMP1_CSR
COMP2 output
COMP2_CSR
26.6 COMP registers
26.6.1 Comparator 1 control and status register (COMP1_CSR)
The COMP1_CSR is the Comparator 1 control/status register. It contains all the bits /flags
related to comparator1.
Address offset: 0x00
System reset value: 0x0000 0000
31 30 29
LOCK VALUE Res. Res.
rs r
15 14 13
POLA
Res. Res. Res.
RITY
rw
Bit 31 LOCK: COMP1_CSR register lock bit
Bit 30 VALUE: Comparator 1 output status bit
Bits 29: Reserved, must be kept at reset value.
Bit 23 SCALEN: Voltage scaler enable bit
Table 176. Interrupt control bits
Enable control
bit
VALUE in
through EXTI
VALUE in
through EXTI
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
This bit is set by software and cleared by a hardware system reset. It locks the whole
content of the comparator 1 control register, COMP1_CSR[31:0].
0: COMP1_CSR[31:0] for comparator 1 are read/write
1: COMP1_CSR[31:0] for comparator 1 are read-only
This bit is read-only. It reflects the current comparator 1 output taking into account
POLARITY bit effect.
This bit is set and cleared by software. This bit enable the outputs of the V
available on the minus input of the Comparator 1.
0: Bandgap scaler disable (if SCALEN bit of COMP2_CSR register is also reset)
1: Bandgap scaler enable
Exit from Sleep
mode
yes
yes
24 23 22
SCAL BRG
Res.
EN EN
rw rw
8 7 6
INP
Res. INMSEL
SEL.
rw
RM0432 Rev 6
Comparator (COMP)
Exit from Stop
modes
yes
yes
21 20 19 18
Res. BLANKING
rw
5 4 3 2
PWRMODE
rw rw
REFINT
Exit from
Standby mode
N/A
N/A
17 16
HYST
rw
1 0
Res. EN
rw
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