ST STM32L4+ Series Reference Manual page 855

RM0432
or
Datarate samples s ⁄
Maximum output data rate in case of parallel data input:
Datarate samples s ⁄
or
Datarate samples s ⁄
or
Datarate samples s ⁄
where: f
The right bit-shift of final data is performed in this module because the final data width is 24-
bit and data coming from the processing path can be up to 32 bits. This right bit-shift is
configurable in the range 0-31 bits for each selected input channel (see DTRBS[4:0] bits in
DFSDM_CHyCFGR2 register). The right bit-shift is rounding the result to nearest integer
value. The sign of shifted result is maintained - to have valid 24-bit signed format of result
data.
In the next step, an offset correction of the result is performed. The offset correction value
(OFFSET[23:0] stored in register DFSDM_CHyCFGR2) is subtracted from the output data
for a given channel. Data in the OFFSET[23:0] field is set by software by the appropriate
calibration routine.
Due to the fact that all operations in digital processing are performed on 32-bit signed
registers, the following conditions must be fulfilled not to overflow the result:
FORD
FOSR
2 . FOSR
Note: In case of filter and integrator bypass (IOSR[7:0]=0, FOSR[9:0]=0), the input data rate
(f
DATAIN_RATE
f
DATAIN_RATE
where f
APB
28.4.14 Signed data format
Each DFSDM input serial channel can be connected to one external Σ∆ modulator. An
external Σ∆ modulator can have 2 differential inputs (positive and negative) which can be
used for a differential or single-ended signal measurement.
A Σ∆ modulator output is always assumed in a signed format (a data stream of zeros and
ones from a Σ∆ modulator represents values -1 and +1).
f
CKIN
-------------------------------
=
F
OSR
------------------------------------------------------------------------------------------------------ -
=
F
OSR
------------------------------------------------------------------------------- -
=
F
OSR
f
DATAIN_RATE
----------------------------------- -
=
F
OSR
...input data rate from ADC or from CPU/DMA
DATAIN_RATE
31
. IOSR <= 2
2 31
. IOSR <= 2 ... for FastSinc filter)
) must be limited to be able to read all output data:
≤ f
APB
is the bus frequency to which the DFSDM peripheral is connected.
Digital filter for sigma delta modulators (DFSDM)
...FAST = 1
⋅
I
OSR
f
DATAIN_RATE
⋅ ( ) (
I – 1 + F +
OSR ORD
f
DATAIN_RATE
⋅ ( ) (
I – 1 + 4 + 2 + 1
OSR
...FAST=1 or any filter bypass case F
⋅
I
OSR
x
... for Sinc filters, x = 1..5)
RM0432 Rev 6
...FAST = 0, Sincx filter
)
F + 1
ORD
...FAST = 0, FastSinc filter
)
( )
= 1
OSR
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