ST STM32L4+ Series Reference Manual page 701

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Bit 2 DFSDMCFG: DFSDM mode configuration

This bit is set and cleared by software to enable the DFSDM mode. It is effective only when

0: DFSDM mode disabled

1: DFSDM mode enabled

Note: To make sure no conversion is ongoing, the software is allowed to write this bit only when

ADSTART= 0 and JADSTART= 0.

Bit 1 DMACFG: Direct memory access configuration

This bit is set and cleared by software to select between two DMA modes of operation and is

effective only when DMAEN=1.

0: DMA One Shot mode selected

1: DMA Circular mode selected

For more details, refer to

Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which

ensures that no conversion is ongoing).

In dual-ADC modes, this bit is not relevant and replaced by control bit DMACFG of the

ADCx_CCR register.

Bit 0 DMAEN: Direct memory access enable

This bit is set and cleared by software to enable the generation of DMA requests. This allows to use

the DMA to manage automatically the converted data. For more details, refer to

conversions using the

0: DMA disabled

1: DMA enabled

Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which

ensures that no conversion is ongoing).

In dual-ADC modes, this bit is not relevant and replaced by control bits MDMA[1:0] of the

ADCx_CCR register.

ADC configuration register 2 (ADC_CFGR2)

Address offset: 0x10

Reset value: 0x0000 0000

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:17 Reserved, must be kept at reset value.

Bits 16:11 Reserved, must be kept at reset value.

Section : Managing conversions using the DMA

RM0432 Rev 6

Analog-to-digital converters (ADC)

Section : Managing

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