ST STM32L4+ Series Reference Manual page 162

Embedded Flash memory (FLASH)
3.7.10 Flash PCROP1 End address register (FLASH_PCROP1ER)
Address offset: 0x28
Reset value: 0xXFFX XXXX. Register bits are loaded with values from Flash memory at
OBL.
Access: no wait state when no Flash memory operation is on going; word, half-word access.
PCROP_RDP bit can be accessed with byte access.
31 30 29
PCROP
Res. Res.
_RDP
rs
15 14 13
rw rw rw
Bits 30:17 Reserved, must be kept cleared
3.7.11 Flash WRP1 area A address register (FLASH_WRP1AR)
Address offset: 0x2C
Reset value: 0xFFXX FFXX. Register bits are loaded with values from Flash memory at
OBL.
Access: no wait state when no Flash memory operation is on going; word, half-word and
byte access
31 30 29
Res. Res. Res.
15 14 13
Res. Res. Res.
162/2301
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
rw rw rw rw
Bit 31 PCROP_RDP: PCROP area preserved when RDP level decreased
This bit is set only. It is reset after a full mass erase due to a change of RDP
from Level 1 to Level 0.
0: PCROP area is not erased when the RDP level is decreased from Level 1 to
Level 0.
1: PCROP area is erased when the RDP level is decreased from Level 1 to
Level 0 (full mass erase).
Bits 16:0 PCROP1_END: Bank 1 PCROP area end offset
DBANK=1
PCROP1_END contains the last double-word of the bank 1 PCROP area.
DBANK=0
PCROP1_END contains the last 2x double-word PCROP area for all memory.
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
Res. Res. Res. Res.
24 23 22
Res. Res. Res.
8 7 6
PCROP1_END[16:0]
rw rw rw
24 23 22
Res.
rw rw
8 7 6
Res.
rw rw
RM0432 Rev 6
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
rw rw rw rw
21 20 19 18
WRP1A_END[7:0]
rw rw rw rw
5 4 3 2
WRP1A_STRT[7:0]
rw rw rw rw
RM0432
17 16
PCRO
Res. P1_EN
D
rw
1 0
rw rw
17 16
rw rw
1 0
rw rw