ST STM32L4+ Series Reference Manual page 588

Octo-SPI interface (OCTOSPI)
19.6.5 OCTOSPI device configuration register 4 (OCTOSPI_DCR4)
Address offset: 0x0014
Reset value: 0x0000 0000
31 30 29 28
rw rw rw rw
15 14 13 12
rw rw rw rw
Bits 31:0 REFRESH[31:0]: Refresh rate
This field enables the refresh rate feature.
The nCS is released every REFRESH+1 clock cycles for writes, and REFRESH+4 clock
cycles for reads.
Note: These two values can be extended with few clock cycles when refresh occurs during a
0: Refresh disabled
others: Maximum communication length is set to REFRESH+1 clock cycles.
19.6.6 OCTOSPI status register (OCTOSPI_SR)
Address offset: 0x0020
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res.
r
Bits 31:14 Reserved, must be kept at reset value.
Bits 13:8 FLEVEL[5:0]: FIFO level
This field gives the number of valid bytes that are being held in the FIFO. FLEVEL=0 when
the FIFO is empty, and 32 when it is full.
In Automatic-status polling mode, FLEVEL is zero.
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 BUSY: Busy
This bit is set when an operation is ongoing. It is cleared automatically when the operation
with the external device is finished and the FIFO is empty.
Bit 4 TOF: Timeout flag
This bit is set when timeout occurs. It is cleared by writing 1 to CTOF.
588/2301
27 26 25
rw rw rw
11 10 9
rw rw rw
byte transmission in single, dual or quad mode, because the byte transmission must be
completed.
27 26 25
Res. Res. Res.
11 10 9
FLEVEL[5:0]
r r r r
24 23 22
REFRESH[31:16]
rw rw rw
8 7 6
REFRESH[15:0]
rw rw rw
24 23 22
Res. Res. Res. Res.
8 7 6
Res. Res. BUSY
r
RM0432 Rev 6
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
21 20 19 18
Res. Res. Res.
5 4 3 2
TOF SMF FTF
r r r r
RM0432
17 16
rw rw
1 0
rw rw
17 16
Res. Res.
1 0
TCF TEF
r r