ST STM32L4+ Series Reference Manual page 978

DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only
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Define the vertical line configuration:
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Figure 238
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line, a malfunction occurs. This phenomenon can be avoided by configuring the
DSI Host to go to Low-Power once per line.
Configure the horizontal sync duration (DSI_VHSACR.HSA) with the time taken by
a LTDC Horizontal Sync Active period measured in cycles of lane byte clock
(normally a period of 8 ns).
Configure the horizontal back porch duration (DSI_VHBPCR.HBP) with the time
taken by the LTDC Horizontal Back Porch period measured in cycles of lane byte
clock (normally a period of 8 ns). Special attention should be given to the
calculation of this parameter.
Configure the vertical sync duration (DSI_VVSACR.VSA) with the number of lines
existing in the LTDC Vertical Sync Active period.
Configure the vertical back porch duration (DSI_VVBPCR.VBP) with the number
of lines existing in the LTDC Vertical Back Porch period.
Configure the vertical front porch duration (DSI_VVFPCR.VFP) with the number of
lines existing in the LTDC Vertical Front Porch period.
Configure the vertical active duration (DSI_VVACR.VA) with the number of lines
existing in the LTDC Vertical Active period.
illustrates the steps for configuring the DPI packet transmission.
RM0432 Rev 6
RM0432