ST STM32L4+ Series Reference Manual page 135

RM0432
Bit 22 DBANK:
0: Single-bank mode with 128 bits data read width
1: Dual-bank mode with 64 bits data
This bit can be written only when PCROP1/2 is disabled.
Bit 21 DB1M:
For STM32L4Rxxx and STM32L4Sxxx devices:
Dual-bank on 1-Mbyte Flash memory devices
0: 1 Mbyte single Flash contiguous address in Bank1
1: 1 Mbyte dual-bank Flash with contiguous addresses
For STM32L4P5xx and STM32L4Q5xx devices:
Dual-bank on 512 Kbytes Flash memory devices
0: 512 Kbytes single Flash contiguous address in Bank1
1: 512 Kbytes Dual-bank Flash with contiguous addresses
Bit 20 BFB2: Dual-bank boot
0: Dual-bank boot disable
1: Dual-bank boot enable
Bit 19 WWDG_SW: Window watchdog selection
0: Hardware window watchdog
1: Software window watchdog
Bit 18 IWDG_STDBY: Independent watchdog counter freeze in Standby mode
0: Independent watchdog counter is frozen in Standby mode
1: Independent watchdog counter is running in Standby mode
Bit 17 IWDG_STOP: Independent watchdog counter freeze in Stop mode
0: Independent watchdog counter is frozen in Stop mode
1: Independent watchdog counter is running in Stop mode
Bit 16 IDWG_SW: Independent watchdog selection
0: Hardware independent watchdog
1: Software independent watchdog
Bit 15 Reserved, must be kept at reset value.
Bit 14 nRST_SHDW:
0: Reset generated when entering the Shutdown mode
1: No reset generated when entering the Shutdown mode
Bit 13 nRST_STDBY
0: Reset generated when entering the Standby mode
1: No reset generate when entering the Standby mode
Bit 12 nRST_STOP
0: Reset generated when entering the Stop mode
1: No reset generated when entering the Stop mode
RM0432 Rev 6
Embedded Flash memory (FLASH)
135/2301
168