ST STM32L4+ Series Reference Manual page 279

RM0432
Bit 20 OSPIMRST: OctoSPI IO manager reset
Bit 19 Reserved, must be kept at reset value.
Bit 18 RNGRST: Random number generator reset
Bit 17 HASHRST: Hash reset
Set and cleared by software.
0: No effect
1: Reset HASH
Bit 16 AESRST: AES hardware accelerator reset
Bit 15 PKARST: PKA reset
Bit 14 DCMIRST: DCMI or PSSI reset (DCMI or PSSI depending on which interface is active)
Set and cleared by software
0: No effect
1: Reset DCMI/PSSI interface
Bit 13 ADCRST: ADC reset
Bit 12 OTGFSRST: USB OTG FS reset
Bits 11:9 Reserved, must be kept at reset value.
Bit 8 GPIOIRST: IO port I reset
Set and cleared by software
Bit 7 GPIOHRST: IO port H reset
Set and cleared by software.
0: No effect
1: Reset OctoSPI IO manager
Set and cleared by software.
0: No effect
1: Reset RNG
Set and cleared by software.
0: No effect
1: Reset AES
Set and cleared by software.
0: No effect
1: Reset PKA
Set and cleared by software.
0: No effect
1: Reset ADC interface
Set and cleared by software.
0: No effect
1: Reset USB OTG FS
0: No effect
1: Reset IO port I
Set and cleared by software.
0: No effect
1: Reset IO port H
RM0432 Rev 6
Reset and clock control (RCC)
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