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DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only
30.15.16 DSI Host Video HBP Configuration Register (DSI_VHBPCR)
Address offset: 0x004C
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31: 12 Reserved, must be kept at reset value
Bits 11: 0 HBP: Horizontal Back-Porch duration
30.15.17 DSI Host Video Line Configuration Register (DSI_VLCR)
Address offset: 0x0050
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Bits 31: 15 Reserved, must be kept at reset value
Bits 14: 0 HLINE: Horizontal Line duration
30.15.18 DSI Host Video VSA Configuration Register (DSI_VVSACR)
Address offset: 0x0054
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
994/2301
27
26
25
Res.
Res.
Res.
11
10
9
This fields configures the Horizontal Back-Porch period in lane byte clock cycles.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
This fields configures the total of the Horizontal Line period (HSA+HBP+HACT+HFP)
counted in lane byte clock cycles.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
24
23
22
21
Res.
Res.
Res.
Res.
8
7
6
5
HBP[11:0]
rw
24
23
22
Res.
Res.
Res.
8
7
6
HLINE[14:0]
rw
24
23
22
Res.
Res.
Res.
8
7
6
RM0432 Rev 6
20
19
18
Res.
Res.
Res.
4
3
2
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
VSA[9:0]
rw
RM0432
17
16
Res.
Res.
1
0
17
16
Res.
Res.
1
0
17
16
Res.
Res.
1
0
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