ST STM32L4+ Series Reference Manual page 468

Nested vectored interrupt controller (NVIC)
15 Nested vectored interrupt controller (NVIC)
15.1 NVIC main features
•
95 maskable interrupt channels (not including the sixteen Cortex
interrupt lines)
•
16 programmable priority levels (4 bits of interrupt priority are used)
•
Low-latency exception and interrupt handling
•
Power management control
• Implementation of System Control Registers
The NVIC and the processor core interface are closely coupled, which enables low latency
interrupt processing and efficient processing of late arriving interrupts.
All interrupts including the core exceptions are managed by the NVIC. For more information
on exceptions and NVIC programming, refer to the PM0214 programming manual for
Cortex TM
15.2 SysTick calibration value register
The SysTick calibration value is set to 0x4000 3A97, which gives a reference time base of
1 ms with the SysTick clock set to 15 MHz (max f
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