ST STM32L4+ Series Reference Manual page 296

Reset and clock control (RCC)
31 30 29
Res. Res. Res.
15 14 13
Res. Res. Res. CRCSMEN
Bits 31:19 Reserved, must be kept at reset value.
Bit 18 GFXMMUSMEN: GFXMMU clock enable during Sleep and Stop modes.
Bit 17 DMA2DSMEN: DMA2D clock enable during Sleep and Stop modes
Set and cleared by software
0: DMA2D clocks disabled by the clock gating
1: DMA2D clocks enabled by the clock gating
Bit 16 TSCSMEN: Touch Sensing Controller clocks enable during Sleep and Stop modes
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 CRCSMEN: CRC clocks enable during Sleep and Stop modes
Bits 11:10 Reserved, must be kept at reset value.
Bit 9 SRAM1SMEN: SRAM1 interface clocks enable during Sleep and Stop modes
Bit 8 FLASHSMEN: Flash memory interface clocks enable during Sleep and Stop modes
Bits 7:3 Reserved, must be kept at reset value.
296/2301
28 27 26
Res. Res. Res. Res.
12 11 10
SRAM1
Res. Res.
SMEN
rw
Set and cleared by software
0: GFXMMU clocks disabled by the clock gating
1: GFXMMU clocks enabled by the clock gating
Set and cleared by software.
0: TSC clocks disabled by the clock gating
1: TSC clocks enabled by the clock gating
Set and cleared by software.
0: CRC clocks disabled by the clock gating
1: CRC clocks enabled by the clock gating
Set and cleared by software.
0: SRAM1 interface clocks disabled by the clock gating
1: SRAM1 interface clocks enabled by the clock gating
Set and cleared by software.
0: Flash memory interface clocks disabled by the clock gating
modes
1: Flash memory interface clocks enabled by the clock gating
modes
25 24 23 22
Res. Res. Res.
9 8 7 6
FLASH
Res. Res.
SMEN
rw rw
(1)
(1)
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
RM0432 Rev 6
21 20 19 18
GFXM
Res. Res. Res. MUSM
EN
rw
5 4 3
DMAM
Res. Res. Res. UX1S
MEN
during Sleep and Stop modes
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop
(1)
during Sleep and Stop
RM0432
17 16
DMA2D TSCS
SMEN MEN
rw rw
2 1 0
DMA2S DMA1
MEN SMEN
rw rw