ST STM32L4+ Series Reference Manual page 883

RM0432
Table 191. DFSDM register map and reset values (continued)
Register
Offset
name
DFSDM_
CH5CFGR1
0xA0
reset value
DFSDM_
CH5CFGR2
0xA4
reset value 0
DFSDM_
CH5AWSCDR
0xA8
reset value
DFSDM_
CH5WDATR
0xAC
reset value
DFSDM_
CH5DATINR
0xB0
reset value 0
DFSDM_
CH5DLYR
0xB4
reset value
0xB8 -
Reserved
0xBC
DFSDM_
CH6CFGR1
0xC0
reset value
DFSDM_
CH6CFGR2
0xC4
reset value 0
DFSDM_
CH6AWSCDR
0xC8
reset value
DFSDM_
CH6WDATR
0xCC
reset value
DFSDM_
CH6DATINR
0xD0
reset value 0
DFSDM_
CH6DLYR
0xD4
reset value
0xD8 -
Reserved
0xDC
0 0 0 0 0 0 0 0 0
0 0
INDAT1[15:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0
INDAT1[15:0]
0 0 0 0 0 0 0 0 0
Digital filter for sigma delta modulators (DFSDM)
0 0
OFFSET[23:0]
0 0 0 0 0 0 0 0
AWFOSR[4:0] BKSCD[3:0]
0 0 0 0 0 0 0
0 0
0 0 0 0 0 0 0 0
0 0
OFFSET[23:0]
0 0 0 0 0 0 0 0
AWFOSR[4:0] BKSCD[3:0]
0 0 0 0 0 0 0
0 0
0 0 0 0 0 0 0 0
RM0432 Rev 6
0 0 0 0 0 0
DTRBS[4:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0
WDATA[15:0]
0 0 0 0 0 0 0 0 0
INDAT0[15:0]
0 0 0 0 0 0 0 0 0
0
0 0 0 0 0 0
DTRBS[4:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0
WDATA[15:0]
0 0 0 0 0 0 0 0 0
INDAT0[15:0]
0 0 0 0 0 0 0 0 0
0
0 0 0 0
0 0
SCDT[7:0]
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
PLSSKP[5:0]
0 0 0 0 0
0 0 0 0
0 0
SCDT[7:0]
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
PLSSKP[5:0]
0 0 0 0 0
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