ST STM32L4+ Series Reference Manual page 964

DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only
30.12.2 Special D-PHY operations
The DSI Wrapper have some control bit to force the D-PHY in some particular state and/or
behavior.
Forcing lane state
It's possible to force the data lane and/or the clock lane in TX Stop mode through the bits
FTXSMDL and FTXSMCL of the DSI_WPCR1 register.
Setting this bits causes the respective lane module to immediately jump in transmit control
mode and to begin transmitting a stop state (LP-11).
This feature can be used to go back in TX ode after a wrong BTA sequence.
Forcing Low-Power receiver in Low-Power mode
The FLPRXLPM bit of the DSI_WPCR1 register enables the Low-Power mode of the low
power receiver (LPRX). When set, the LPRX operates in Low-Power mode all the time.
When not set, the LPRX operates in Low-Power mode during ULPS only.
Disabling turn of data lane
When set, the TDDL bit of the DSI_WPCR0 register forces the data lane to remain in
reception mode even if a Bus Turn Around request (BTA) is received from the other side.
30.12.3 Special Low-power D-PHY functions
The embedded D-PHY offers two specific features to optimize consumption.
Pull-down on lanes
The D-PHY embedded pull-down on each lane to prevent from floating states when the
lanes are unused.
When set, the PDEN bit of the DSI_WPCR0 register enables the pull-down on the lanes.
Disabling contention detection on data lanes
The contention detector on the data lane can be turned off to lower the overall D-PHY
consumption.
When set, the CDOFFDL bit of the DSI_WPCR0 register disables the contention detection
on data lanes.
This can be used in forward Escape mode to reduce the static power consumption.
964/2301 RM0432 Rev 6
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