ST STM32L4+ Series Reference Manual page 485

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Pending register 1 (EXTI_PR1)

Address offset: 0x14

Reset value: undefined

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:18 PIFx: Pending interrupt flag on line x (x = 22 to 18)

Bits 16:0 PIFx: Pending interrupt flag on line x (x = 16 to 0)

Interrupt mask register 2 (EXTI_IMR2)

Address offset: 0x20

Reset value: 0x0000 0187

Bits 31:8 Reserved, must be kept at reset value

The reset value for the direct lines (line 17, lines from 23 to 34, line 39, line 40) is set to '1' in

order to enable the interrupt by default.

0: No trigger request occurred

1: Selected trigger request occurred

This bit is set when the selected edge event arrives on the interrupt line. This bit

is cleared by writing a '1' to the bit.

Bit 17 Reserved, must be kept at reset value.

0: No trigger request occurred

1: Selected trigger request occurred

This bit is set when the selected edge event arrives on the interrupt line. This bit

is cleared by writing a '1' to the bit.

Bits 8:0 IMx: Interrupt mask on line x (x = 40 to 32)

0: Interrupt request from line x is masked

1: Interrupt request from line x is not masked

Extended interrupts and events controller (EXTI)

RM0432 Rev 6

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