ST STM32L4+ Series Reference Manual page 305

RM0432
Bit 17 TIM16SMEN: TIM16 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: TIM16 timer clocks disabled by the clock gating
1: TIM16 timer clocks enabled by the clock gating
Bit 16 TIM15SMEN: TIM15 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: TIM15 timer clocks disabled by the clock gating
1: TIM15 timer clocks enabled by the clock gating
Bit 15 Reserved, must be kept at reset value.
Bit 14 USART1SMEN: USART1clocks enable during Sleep and Stop modes
Set and cleared by software.
0: USART1clocks disabled by the clock gating
1: USART1clocks enabled by the clock gating
Bit 13 TIM8SMEN: TIM8 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: TIM8 timer clocks disabled by the clock gating
1: TIM8 timer clocks enabled by the clock gating
Bit 12 SPI1SMEN: SPI1 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SPI1 clocks disabled by the clock gating during
1: SPI1 clocks enabled by the clock gating during
Bit 11 TIM1SMEN: TIM1 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: TIM1 timer clocks disabled by the clock gating
1: TIM1P timer clocks enabled by the clock gating
Bits 10:1 Reserved, must be kept at reset value.
Bit 0 SYSCFGSMEN: SYSCFG + COMP + VREFBUF clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SYSCFG + COMP + VREFBUF clocks disabled by the clock gating
Stop modes
1: SYSCFG + COMP + VREFBUF clocks enabled by the clock gating
Stop modes
1. This register only configures the clock gating, not the clock source itself. Most of the peripherals are clocked by a single
clock (AHB or APB clock), which is always disabled in Stop mode. In this case setting the bit has no effect in Stop mode.
6.4.28 Peripherals independent clock configuration register (RCC_CCIPR)
Address: 0x88
Reset value: 0x0000 0000
Access: no wait states, word, half-word and byte access
(1)
(1)
(1)
(1)
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
(1)
(1)
(1)
(1)
(1)
RM0432 Rev 6
Reset and clock control (RCC)
during Sleep and Stop modes
during Sleep and Stop modes
during Sleep and Stop modes
during Sleep and Stop modes
during Sleep and Stop modes
during Sleep and Stop modes
Sleep and Stop modes
Sleep and Stop modes
during Sleep and Stop modes
during Sleep and Stop modes
(1)
during Sleep and
(1)
during Sleep and
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