ST STM32L4+ Series Reference Manual page 733

RM0432
XOR
X
The LFSR value, that may be masked partially or totally by means of the MAMPx[3:0] bits in
the DAC_CR register, is added up to the DAC_DHRx contents without overflow and this
value is then transferred into the DAC_DORx register.
If LFSR is 0x0000, a '1 is injected into it (antilock-up mechanism).
It is possible to reset LFSR wave generation by resetting the WAVEx[1:0] bits.
Figure 163. DAC conversion (SW trigger enabled) with LFSR wave generation
APB1_CLK
DHR
DOR
SWTRIG
Note: The DAC trigger must be enabled for noise generation by setting the TENx bit in the
DAC_CR register.
Figure 162. DAC LFSR register calculation algorithm
12
11 10 9
0x00
6
X
8 7 6 5
12
NOR
0xAAA
RM0432 Rev 6
Digital-to-analog converter (DAC)
4
X X
4 3 2 1
0xD55
0
X
0
ai14713c
ai14714b
733/2301
762