ST STM32L4+ Series Reference Manual page 331

RM0432
7.7.5 CRS register map
Offset Register
CRS_CR
0x00
Reset value
CRS_CFGR
0x04
Reset value 0
CRS_ISR
0x08
Reset value 0
CRS_ICR
0x0C
Reset value
1. The TRIM bitfield can be one bit less. Refer to
Refer to
Table 42. CRS register map and reset values
SYNC SYNC
SRC DIV
[1:0] [2:0]
1 0 0 0 0 0
FECAP[15:0]
0 0 0 0 0 0 0 0
Section 7.3: CRS implementation
Section 2.2 on page 91
FELIM[7:0]
0 1 0 0 0 1 0 1
0 0 0 0 0 0 0 0
for the register boundary addresses.
RM0432 Rev 6
Clock recovery system (CRS)
TRIM[5:0]
1 0 0 0 0 0 0 0
RELOAD[15:0]
0 1 1 1 0 1 1 0
0 0 0
for details.
0 0 0 0 0 0 0
1 1 1 1 1 1 1
0 0 0 0
0 0 0 0
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