ST STM32L4+ Series Reference Manual page 716

Analog-to-digital converters (ADC)
21.6.22 ADC Calibration Factors (ADC_CALFACT)
Address offset: 0xB4
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:16 CALFACT_D[6:0]: Calibration Factors in differential mode
These bits are written by hardware or by software.
Once a differential inputs calibration is complete, they are updated by hardware with the calibration
factors.
Software can write these bits with a new calibration factor. If the new calibration factor is different
from the current one stored into the analog ADC, it will then be applied once a new differential
calibration is launched.
Note: The software is allowed to write these bits only when ADEN=1, ADSTART=0 and JADSTART=0
(ADC is enabled and no calibration is ongoing and no conversion is ongoing).
Bits 15:7 Reserved, must be kept at reset value.
Bits 6:0 CALFACT_S[6:0]: Calibration Factors In single-ended mode
These bits are written by hardware or by software.
Once a single-ended inputs calibration is complete, they are updated by hardware with the
calibration factors.
Software can write these bits with a new calibration factor. If the new calibration factor is different
from the current one stored into the analog ADC, it will then be applied once a new single-ended
calibration is launched.
Note: The software is allowed to write these bits only when ADEN=1, ADSTART=0 and JADSTART=0
(ADC is enabled and no calibration is ongoing and no conversion is ongoing).
21.7 ADC common registers
These registers define the control and status registers common to master and slave ADCs:
21.7.1 ADC common status register (ADC_CSR)
Address offset: 0x00 (this offset address is relative to the master ADC base address +
0x300)
Reset value: 0x0000 0000
This register provides an image of the status bits of the different ADCs. Nevertheless it is
read-only and does not allow to clear the different status bits. Instead each status bit must
be cleared by writing 0 to it in the corresponding ADC_ISR register.
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28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
24 23 22 21
Res. Res.
rw rw
8 7 6
Res. Res.
rw rw
RM0432 Rev 6
20 19 18
CALFACT_D[6:0]
rw rw rw
5 4 3 2
CALFACT_S[6:0]
rw rw rw
RM0432
17 16
rw rw
1 0
rw rw