ST STM32L4+ Series Reference Manual page 159

RM0432
3.7.8 Flash option register (FLASH_OPTR)
Address offset: 0x20
Reset value: 0xFFEF F8AA. Register bits are loaded with values from Flash memory at
OBL.
Access: no wait state when no Flash memory operation is on going; word, half-word and
byte access
31 30 29
Res. Res. Res. Res.
15 14 13
nRST_ nRST_ nRST_
Res.
SHDW STDBY STOP
rw rw
Bits 31:28 Reserved, must be kept at reset value.
28 27 26 25
n nSW SRAM2
BOOT0 BOOT0 _RST
rw rw rw
12 11 10 9
Res. BOR_LEV[2:0]
rw rw rw
Bit 27 nBOOT0: nBOOT0 option bit
0: nBOOT0 = 0
1: nBOOT0 = 1
Bit 26 nSWBOOT0: Software BOOT0
0: BOOT0 taken from the option bit nBOOT0
1: BOOT0 taken from PH3/BOOT0 pin
Bit 25 SRAM2_RST: SRAM2 Erase when system reset
0: SRAM2 erased when a system reset occurs
1: SRAM2 is not erased when a system reset occurs
Bit 24 SRAM2_PE: SRAM2 parity check enable
0: SRAM2 parity check enable
1: SRAM2 parity check disable
Bit 23 nBOOT1: Boot configuration
Together with the BOOT0 pin, this bit selects boot mode from the Flash main
memory, SRAM1 or the System memory. Refer to
configuration.
Bit 22 DBANK:
0: Single-bank mode with 128 bits data read width
1: Dual-bank mode with 64 bits data
This bit can only be written when PCROPA/B is disabled.
24 23 22
SRAM2 nBOOT
DBANK DB1M
_PE 1
rw rw rw
8 7 6
rw rw rw
RM0432 Rev 6
Embedded Flash memory (FLASH)
21 20 19 18
WWDG IWGD_
BFB2
_SW STDBY
rw rw rw rw
5 4 3 2
RDP[7:0]
rw rw rw rw
Section 2.6: Boot
17 16
IWDG_
IWDG_
SW
StOP
rw rw
1 0
rw rw
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