ST STM32L4+ Series Reference Manual page 649

RM0432
Figure 115. Single conversions of a sequence, hardware trigger
ADSTART
EOC
EOS
(1)
TRGX
(2)
ADC state
ADC_DR
by s/w
1. TRGx (over-frequency) is selected as trigger source, EXTEN[1:0] = 01, CONT = 0
2. Channels selected = 1, 2, 3, 4; AUTDLY=0.
Figure 116. Continuous conversions of a sequence, hardware trigger
ADSTART
EOC
EOS
ADSTP
(1)
TRGx
(2)
ADC
RDY
ADC_DR
by s/w
1. TRGx is selected as trigger source, EXTEN[1:0] = 10, CONT = 1
2. Channels selected = 1, 2, 3, 4; AUTDLY=0.
CH1 CH2
RDY
D1
by h/w triggered
CH1 CH2 CH3
D1 D2
by h/w triggered
CH3 CH4 READY
D2 D3
ignored
CH4 CH1 CH2
D3 D4 D1
ignored
RM0432 Rev 6
Analog-to-digital converters (ADC)
CH1 CH2 CH3
D4 D1 D2
Indicative timings
STOP
CH3 CH4 CH1
D2 D3 D4
Not in scale timings
CH4 RDY
D3 D4
MS31013V2
RDY
MS31014V2
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