ST STM32L4+ Series Reference Manual page 218

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Power control (PWR)

Bit 4 RRSTP: SRAM3 retention in Stop 2 mode

Bit 3 Reserved, must be kept at reset value.

Bits 2:0 LPMS[2:0]: Low-power mode selection

Note: If LPR bit is set, Stop 2 mode cannot be selected and Stop 1 mode shall be entered

Power control register 2 (PWR_CR2)

Address offset: 0x04

Reset value: 0x0000 0000 (This register is reset when exiting the Standby mode)

Bits 31:11 Reserved, must be kept at reset value.

Bit 8 Reserved, must be kept at reset value.

Bit 7 PVME4: Peripheral voltage monitoring 4 enable:

0: SRAM3 is powered off in Stop 2 mode (SRAM3 content is lost)

1: SRAM3 is powered in Stop 2 mode (RAM3 content is kept).

These bits select the low-power mode entered when CPU enters the Deepsleep mode.

000: Stop 0 mode

001: Stop 1 mode

010: Stop 2 mode

011: Standby mode

1xx: Shutdown mode

instead of Stop 2.

In Standby mode, SRAM2 can be preserved or not, depending on RRS bit configuration

USB supply valid

This bit is used to validate the

Setting this bit is mandatory to use the USB OTG_FS peripheral. If

present in the application, the PVM can be used to determine whether this supply is ready or

is not present. Logical and electrical isolation is applied to ignore this supply.

Independent I/Os supply valid

This bit is used to validate the

Setting this bit is mandatory to use PG[15:2]. If

application, the PVM can be used to determine whether this supply is ready or not.

is not present. Logical and electrical isolation is applied to ignore this supply.

monitoring vs. 2.2V threshold) disable.

monitoring vs. 2.2V threshold) enable.

PVME4 PVME3 PVME2 PVME1

supply for electrical and logical isolation purpose.

supply for electrical and logical isolation purpose.

RM0432 Rev 6

is not always present in the

is not always

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