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RM0432
24.5.3
DCMI raw interrupt status register (DCMI_RIS)
DCMI_RIS gives the raw interrupt status and is accessible in read only. When read, this
register returns the status of the corresponding interrupt before masking with the DCMI_IER
register value.
Address offset: 0x08
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:5 Reserved, must be kept at reset value.
Bit 4 LINE_RIS: Line raw interrupt status
Bit 3 VSYNC_RIS: DCMI_VSYNC raw interrupt status
Bit 2 ERR_RIS: Synchronization error raw interrupt status
Note: This bit is available only in embedded synchronization mode.
Bit 1 OVR_RIS: Overrun raw interrupt status
Bit 0 FRAME_RIS: Capture complete raw interrupt status
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
This bit gets set when the DCMI_HSYNC signal changes from the inactive state to the
active state. It goes high even if the line is not valid.
In the case of embedded synchronization, this bit is set only if the CAPTURE bit in
DCMI_CR is set.
It is cleared by setting the LINE_ISC bit of the DCMI_ICR register.
This bit is set when the DCMI_VSYNC signal changes from the inactive state to the active
state.
In the case of embedded synchronization, this bit is set only if the CAPTURE bit is set in
DCMI_CR.
It is cleared by setting the VSYNC_ISC bit of the DCMI_ICR register.
0: No synchronization error detected
1: Embedded synchronization characters are not received in the correct order.
This bit is valid only in the embedded synchronization mode. It is cleared by setting the
ERR_ISC bit of the DCMI_ICR register.
0: No data buffer overrun occurred
1: A data buffer overrun occurred and the data FIFO is corrupted.
The bit is cleared by setting the OVR_ISC bit of the DCMI_ICR register.
0: No new capture
1: A frame has been captured.
This bit is set when a frame or window has been captured.
In case of a cropped window, this bit is set at the end of line of the last line in the crop. It is
set even if the captured frame is empty (e.g. window cropped outside the frame).
The bit is cleared by setting the FRAME_ISC bit of the DCMI_ICR register.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
RM0432 Rev 6
Digital camera interface (DCMI)
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
LINE
VSYNC
ERR
Res.
_RIS
_RIS
_RIS
r
r
r
17
16
Res.
Res.
1
0
OVR
FRAME
_RIS
_RIS
r
r
781/2301
789
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