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Extended interrupts and events controller (EXTI)
16.5.12
Pending register 2 (EXTI_PR2)
Address offset: 0x34
Reset value: undefined
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
488/2301
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Bit 7 PIFx: Pending interrupt flag on line x (x = 35 to 38)
0: No trigger request occurred
1: Selected trigger request occurred
This bit is set when the selected edge event arrives on the interrupt line. This bit
is cleared by writing a '1' into the bit.
Bits 2:0 Reserved, must be kept at reset value.
24
23
22
Res.
Res.
Res.
Res.
8
7
6
Res.
Res.
PIF38
PIF37
rc_w1
rc_w1
RM0432 Rev 6
21
20
19
18
Res.
Res.
Res.
5
4
3
2
PIF36
PIF35
Res.
rc_w1
rc_w1
RM0432
17
16
Res.
Res.
1
0
Res.
Res.
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