ST STM32L4+ Series Reference Manual page 189

RM0432
There are two possible states:
•
Connected: Switch is closed so SMPS powers VDD12
•
Disconnected: Switch is open and VDD12 is disconnected from SMPS output
Proper software management through GPIOs to enable/disable SMPS and to
connect/disconnect SMPS through the switch, is required to conform with the rules
described below. See also
It is mandatory to respect the following rules to avoid any damage or instability on either
digital parts or internal regulators:
•
In Run, Sleep and Stop 0 modes, VDD12 can be connected and should respect
–
–
–
–
•
In all other modes, such as LPRun, LPSleep, Stop 1, Stop 2, Standby and Shutdown
modes, VDD12 must be disconnected from SMPS output. This means that the pin must
be connected to an high impedance output:
–
•
Transitions of VDD12 from connected to disconnected is only allowed when SYSCLK
frequency ≤ 26 MHz to avoid to big voltage drop on main regulator side.
Note: In case of asynchronous reset while having the VDD12 ≤ 1.25 V, VDD12 should switch to
HiZ in less than regulator switching time from Range 2 to Range 1 (~1 us).
Note: On STM32L4P5xx and STM32L4Q5xx devices, VDD12 Range 2 is extended down to
1.00 V for better efficiency, thus following formula applies when bit EXT_SMPS_ON in the
Power control register 4 (PWR_CR4) is set:
Range 2, VCORE = 0.95 V so VDD12 should be greater than 1.00 V
Note: For more details on VDD12 management, refer to AN4978 "Design recommendations for
STM32L4xxxx with external SMPS, for ultra-low-power applications with high performance".
5.1.8 Dynamic voltage scaling management
The dynamic voltage scaling is a power management technique which consists in
increasing or decreasing the voltage used for the digital peripherals (V
the application performance and power consumption needs.
Dynamic voltage scaling to increase V
device performance.
Dynamic voltage scaling to decrease V
save power, particularly in laptop and other mobile devices where the energy comes from a
battery and is thus limited.
• Range 1: High-performance range.
Section 5.1.8: Dynamic voltage scaling
VDD12 < 1.32 V
VDD12 ≥ V + 50 mV giving for main regulator
CORE
Range 1 boost mode, V
but this cannot match previous rule VDD12 < 1.32 V, so it is not a functional use
case with an external SMPS.
Range 1 normal mode, V
Range 2, V = 1.0 V so VDD12 should be greater than 1.05 V
CORE
VDD12 ≥ 1.08 V in Range 2 when 80 MHz ≥ SYSCLK frequency ≥ 26 MHz
VDD12 ≥ 1.14 V in Range 2 when SYSCLK frequency > 80 MHz
VDD12 connected to HiZ (voltage is provided by internal regulators)
=1.28 V so VDD12 should be greater than 1.33 V,
CORE
= 1.2 V so VDD12 should be greater than 1.25 V.
CORE
is known as overvolting. It allows to improve the
CORE
is known as undervolting. It is performed to
CORE
RM0432 Rev 6
Power control (PWR)
management.
), according to
CORE
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