ST STM32L4+ Series Reference Manual page 306

Reset and clock control (RCC)
31 30 29
Res. Res. ADCSEL[1:0]
rw
15 14 13
I2C2SEL[1:0] I2C1SEL[1:0]
rw rw rw
Bit 31 Reserved, must be kept at reset value.
Bit 30 Reserved, must be kept at reset value.
Bits 29:28 ADCSEL[1:0]: ADCs clock source selection
Bits 27:26 CLK48SEL[1:0]: 48 MHz clock source selection
Bits 22:25 Reserved, must be kept at reset value.
Bits 21:20 LPTIM2SEL[1:0]: Low power timer 2 clock source selection
Bits 19:18 LPTIM1SEL[1:0]: Low power timer 1 clock source selection
Bits 17:16 I2C3SEL[1:0]: I2C3 clock source selection
306/2301
28 27 26 25
CLK48SEL[1:0]
rw rw rw
12 11 10 9
LPUART1SEL[1:
UART5SEL[1:0]
0]
rw rw rw rw
These bits are set and cleared by software to select the clock source used by the ADC
interface.
00: No clock selected
01: PLLSAI1 "R" clock (PLLADC1CLK) selected as ADC clock
10: Reserved
11: System clock selected as ADCs clock
These bits are set and cleared by software to select the 48 MHz clock source used by USB
OTG FS, RNG and SDMMC.
00: HSI48 clock selected as 48 MHz clock
01: PLLSAI1 "Q" clock (PLL48M2CLK) selected as 48 MHz clock
10: PLL "Q" clock (PLL48M1CLK) selected as 48 MHz clock
11: MSI clock selected as 48 MHz clock
These bits are set and cleared by software to select the LPTIM2 clock source.
00: PCLK selected as LPTIM2 clock
01: LSI clock selected as LPTIM2 clock
10: HSI16 clock selected as LPTIM2 clock
11: LSE clock selected as LPTIM2 clock
These bits are set and cleared by software to select the LPTIM1 clock source.
00: PCLK selected as LPTIM1 clock
01: LSI clock selected as LPTIM1 clock
10: HSI16 clock selected as LPTIM1 clock
11: LSE clock selected as LPTIM1 clock
These bits are set and cleared by software to select the I2C3 clock source.
00: PCLK selected as I2C3 clock
01: System clock (SYSCLK) selected as I2C3 clock
10: HSI16 clock selected as I2C3 clock
11: Reserved
24 23 22
Res. LPTIM2SEL[1:0]
8 7 6
USART3SEL[1:0
UART4SEL[1:0]
rw rw rw
RM0432 Rev 6
21 20 19 18
LPTIM1SEL[1:0
rw rw rw rw
5 4 3 2
USART2SEL[1:0]
]
rw rw rw rw
RM0432
17 16
I2C3SEL[1:0]
rw rw
1 0
USART1SEL[1:0
]
rw rw