ST STM32L4+ Series Reference Manual page 449

RM0432
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 LW[15:0]: Line watermark
13.5.20 DMA2D AHB master timer configuration register (DMA2D_AMTCR)
Address offset: 0x004C
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:8 DT[7:0]: Dead Time
Bits 7:1 Reserved, must be kept at reset value.
Bit 0 EN: Enable
13.5.21 DMA2D foreground CLUT (DMA2D_FGCLUT[y])
Address offset: 0x0400 + 4*y, y=0..255
Reset value: 0xXXXX XXXX
31 30 29
ALPHA<y>[7:0]
rw rw rw
15 14 13
GREEN<y>[7:0]
rw rw rw
These bits allow to configure the line watermark for interrupt generation.
An interrupt is raised when the last pixel of the watermarked line has been transferred.
These bits can only be written when data transfers are disabled. Once the transfer has
started, they are read-only.
28 27 26 25
Res. Res. Res.
12 11 10 9
DT[7:0]
rw rw rw rw
Dead time value in the AHB clock cycle inserted between two consecutive accesses on
the AHB master port. These bits represent the minimum guaranteed number of cycles
between two consecutive AHB accesses.
Enables the dead time functionality.
28 27 26 25
rw rw rw rw
12 11 10 9
rw rw rw rw
Chrom-ART Accelerator controller (DMA2D)
24 23 22
Res. Res. Res.
8 7 6
Res. Res.
rw
24 23 22
rw rw rw
8 7 6
rw rw rw
RM0432 Rev 6
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
Res. Res. Res. Res.
21 20 19 18
RED<y>[7:0]
rw rw rw rw
5 4 3 2
BLUE<y>[7:0]
rw rw rw rw
17 16
Res. Res.
1 0
Res. EN
rw
17 16
rw rw
1 0
rw rw
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