ST STM32L4+ Series Reference Manual page 936

DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only
when the last pixel of the image is received falls or Command Size (CMDSIZE) limit is
reached.
Synchronization with the LTDC
The DSI wrapper performs the synchronization of the transfer process by :
•
controlling the start/halt of the LTDC.
• making the data flow control between LTDC and DSI Host.
The transfer to refresh the display frame buffer can be trigged
•
manually, setting the LTDC Enable (LTDCEN) bit of the DSI Wapper Control Register
(DSI_WCR).
• automatically when a Tearing Effect (TEIF) event occurs and Automatic Refresh (AR) is
enabled.
The selection between manual and automatic mode is done through the Automatic Refresh
(AR) bit of the DSI Wapper Configuration Register (DSI_WCFGR). In automatic refresh
mode, the LTDC Enable (LTDCEN) bit of the DSI Wapper Control Register (DSI_WCR) is
set automatically by a Tearing Effect (TEIF) event.
Once the transfer of one frame is done whatever in manual or automatic refresh mode, the
DSI Wrapper is halting the TFT Display Controller (LTDC) resetting the LTDC Enable
(LTDCEN) bit of the DSI Wapper Control Register (DSI_WCR) and set the End of Refresh
Interrupt Flag (ERIF) flag of the DSI Wrapper Status Register (DSI_WSR). If the End of
Refresh Interrupt Enable (ERIE) bit of the DSI Wapper Configuration Register
(DSI_WCFGR) is set, an interrupt is generated.
The End of Refresh Interrupt Flag (ERIF) flag of the DSI Wrapper Status Register
(DSI_WSR) can be reset setting the Clear End of Refresh Interrupt Flag (CERIF) bit of the
DSI Wrapper Clear Interrupt Flag Register (DSI_WCIFR).
The halting of the TFT Display Controller (LTDC) by the DSI Wrapper is done synchronously
on a rising edge or a falling edge of VSync according to the VSync Polarity (VSPOL) bit of
the DSI Wapper Configuration Register (DSI_WCFGR).
Support of tearing effect
The DSI specification supports tearing effect function in Command mode displays. It
enables the Host Processor to receive timing accurate information about where the display
peripheral is in the process of reading the content of its frame buffer.
The Tearing effect can be managed through
•
a separate pin which is not covered in the DSI specification
•
the DSI tearing effect functionality: a set_tear_on DCS command should be issued
through the APB interface using the Generic interface registers.
Tearing effect through a GPIO
When the Tearing Effect Source (TESRC) bit of the DSI Wrapper Configuration Register
(DSI_WCFGR) is set, the Tearing effect is signaled through a GPIO.
The polarity of the input signal can be configured by the Tearing Effect Polarity (TEPOL) bit
of the DSI Wrapper Configuration Register (DSI_WCFGR).
When the programmed edge is detected, the Tearing Effect Interrupt Flag (TEIF) bit of the
DSI Wrapper Interrupt and Status Register (DSI_WISR) is set.
936/2301 RM0432 Rev 6
RM0432