ST STM32L4+ Series Reference Manual page 939

RM0432
30.7.1 Packet transmission using the generic interface
The transfer of packets through the APB bus is based on the following conditions:
•
The APB protocol defines that the write and read procedure takes two clock cycles
each to be executed. This means that the maximum input data rate through the APB
interface is always half the speed of the APB clock.
•
The data input bus has a maximum width of 32 bits. This allows for a relation to be
defined between the input APB clock frequency and the maximum bit rate achievable
by the APB interface.
• The DSI link pixel bit rate when using solely APB is (APB clock frequency) * 16 Mbps.
•
When using only the APB interface, the theoretical DSI link maximum bit rate can be
expressed as DSI link maximum bit rate = APB clock frequency (in MHz) * 32 / 2 Mbps.
In this formula, the number 32 represents the APB data bus width, and the division by
two is present because each APB write procedure takes two clock cycles to be
executed.
•
The bandwidth is dependent on the APB clock frequency; the available bandwidth
increases with the clock frequency.
To drive the APB interface to achieve high bandwidth Command mode traffic transported by
the DSI link, the DSI Host should operate in the Command mode only and the APB interface
should be the only data source that is currently in use. Thus, the APB interface has the
entire bandwidth of the DSI link and does not share it with any another input interface
source.
The memory write commands require maximum throughput from the APB interface,
because they contain the most amount of data conveyed by the DSI link. While writing the
packet information, first write the payload of a given packet into the payload FIFO using the
DSI Host Generic Payload Data Register (DSI_GPDR). When the payload data is for the
command parameters, place the first byte to be transmitted in the least significant byte
position of the APB data bus.
After writing the payload, write the packet header into the command FIFO. For more
information about the packet header organization on the 32-bit APB data bus, so that it is
correctly stored inside the Command FIFO.
When the payload data is for a memory write command, it contains pixel information and it
should follow the pixel to byte conversion organization referred in the Annexe A of the DCS
specification.
Figures 210
The memory write commands are conveyed in DCS long packets, encapsulated in a DSI
packet. The DSI specifies that the DCS command should be present in the first payload byte
of the packet. This is also included in the diagrams. In figures
Command can be replaced by the DCS command Write Memory Start and Write Memory
Continue.
DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only
to 214 show how the pixel data should be organized in the APB data write bus.
RM0432 Rev 6
210 to 214, the Write Memory
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