ST STM32L4+ Series Reference Manual page 707

RM0432
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:16 HT3[7:0]: Analog watchdog 3 higher threshold
These bits are written by software to define the higher threshold for the analog watchdog 3.
Refer to
AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx)
Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
Bits 15:8 Reserved, must be kept at reset value.
Bits 7:0 LT3[7:0]: Analog watchdog 3 lower threshold
These bits are written by software to define the lower threshold for the analog watchdog 3.
This watchdog compares the 8-bit of LT3 with the 8 MSB of the converted data.
Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
21.6.11 ADC regular sequence register 1 (ADC_SQR1)
Address offset: 0x30
Reset value: 0x0000 0000
31 30 29
Res. Res. Res.
15 14 13
SQ2[3:0]
rw rw rw
Bits 31:29 Reserved, must be kept at reset value.
Bits 28:24 SQ4[4:0]: 4th conversion in regular sequence
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
Bit 23 Reserved, must be kept at reset value.
Bits 22:18 SQ3[4:0]: 3rd conversion in regular sequence
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
Bit 17 Reserved, must be kept at reset value.
Bits 16:12 SQ2[4:0]: 2nd conversion in regular sequence
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
Bit 11 Reserved, must be kept at reset value.
Section 21.4.29: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH,
28 27 26 25
SQ4[4:0]
rw rw rw rw
12 11 10 9
Res.
rw rw rw
These bits are written by software with the channel number (0 to 18) assigned as the 4th in
the regular conversion sequence.
no regular conversion is ongoing).
These bits are written by software with the channel number (0 to 18) assigned as the 3rd in
the regular conversion sequence.
no regular conversion is ongoing).
These bits are written by software with the channel number (0 to 18) assigned as the 2nd in
the regular conversion sequence.
no regular conversion is ongoing).
24 23 22
Res.
rw rw
8 7 6
SQ1[4:0] Res.
rw rw rw
RM0432 Rev 6
Analog-to-digital converters (ADC)
21 20 19 18
SQ3[4:0]
rw rw rw rw
5 4 3 2
Res.
rw rw
17 16
Res. SQ2[4]
rw
1 0
L[3:0]
rw rw
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