ST STM32L4+ Series Reference Manual page 399

RM0432
DMA
request
MUX input
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Table 54. DMAMUX: assignment of multiplexer inputs to resources
(STM32L4Rxxx and STM32L4Sxxx devices)
Resource
dmamux_req_gen0
dmamux_req_gen1
dmamux_req_gen2
dmamux_req_gen3
ADC1
DAC1
DAC2
TIM6_UP
TIM7_UP
SPI1_RX
SPI1_TX
SPI2_RX
SPI2_TX
SPI3_RX
SPI3_TX
I2C1_RX
I2C1_TX
I2C2_RX
I2C2_TX
I2C3_RX
I2C3_TX
I2C4_RX
I2C4_TX
USART1_RX
USART1_TX
USART2_RX
USART2_TX
USART3_RX
USART3_TX
UART4_RX
UART4_TX
UART5_RX
UART5_TX
LPUART1_RX
LPUART1_TX
SAI1_A
DMA request multiplexer (DMAMUX)
DMA
request Resource
MUX input
44 TIM1_CH3
45 TIM1_CH4
46 TIM1_UP
47 TIM1_TRIG
48 TIM1_COM
49 TIM8_CH1
50 TIM8_CH2
51 TIM8_CH3
52 TIM8_CH4
53 TIM8_UP
54 TIM8_TRIG
55 TIM8_COM
56 TIM2_CH1
57 TIM2_CH2
58 TIM2_CH3
59 TIM2_CH4
60 TIM2_UP
61 TIM3_CH1
62 TIM3_CH2
63 TIM3_CH3
64 TIM3_CH4
65 TIM3_UP
66 TIM3_TRIG
67 TIM4_CH1
68 TIM4_CH2
69 TIM4_CH3
70 TIM4_CH4
71 TIM4_UP
72 TIM5_CH1
73 TIM5_CH2
74 TIM5_CH3
75 TIM5_CH4
76 TIM5_UP
77 TIM5_TRIG
78 TIM15_CH1
79 TIM15_UP
RM0432 Rev 6
DMA
request Resource
MUX input
87 DFSDM1_FLT1
88 DFSDM1_FLT2
89 DFSDM1_FLT3
90 DCMI
91 AES_IN
92 AES_OUT
93 HASH_IN
94 Reserved
95 Reserved
96 Reserved
97 Reserved
98 Reserved
99 Reserved
100 Reserved
101 Reserved
102 Reserved
103 Reserved
104 Reserved
105 Reserved
106 Reserved
107 Reserved
108 Reserved
109 Reserved
110 Reserved
111 Reserved
112 Reserved
113 Reserved
114 Reserved
115 Reserved
116 Reserved
117 Reserved
118 Reserved
119 Reserved
120 Reserved
121 Reserved
122 Reserved
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