ST STM32L4+ Series Reference Manual page 155

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Flash control register (FLASH_CR)

Address offset: 0x14

Reset value: 0xC000 0000

Access: no wait state when no Flash memory operation is on going, word, half-word and

Bits 29:28 Reserved, must be kept at reset value.

Bit 31 LOCK: FLASH_CR Lock

This bit is set only. When set, the FLASH_CR register is locked. It is cleared by

hardware after detecting the unlock sequence.

In case of an unsuccessful unlock operation, this bit remains set until the next

system reset.

Bit 30 OPTLOCK: Options Lock

This bit is set only. When set, all bits concerning user option in FLASH_CR

detecting the unlock sequence. The LOCK bit must be cleared before doing the

unlock sequence for OPTLOCK bit.

In case of an unsuccessful unlock operation, this bit remains set until the next

Bit 27 OBL_LAUNCH: Force the option byte loading

When set to 1, this bit forces the option byte reloading. This bit is cleared only

when the option byte loading is complete. It cannot be written if OPTLOCK is set.

0: Option byte loading complete

1: Option byte loading requested

Bit 26 RDERRIE: PCROP read error interrupt enable

This bit enables the interrupt generation when the RDERR bit in the FLASH_SR

is set to 1.

0: PCROP read error interrupt disabled

1: PCROP read error interrupt enabled

Bit 25 ERRIE: Error interrupt enable

This bit enables the interrupt generation when the OPERR bit in the FLASH_SR

is set to 1.

0: OPERR error interrupt disabled

1: OPERR error interrupt enabled

Bit 24 EOPIE: End of operation interrupt enable

This bit enables the interrupt generation when the EOP bit in the FLASH_SR is

0: EOP Interrupt disabled

1: EOP Interrupt enabled

RM0432 Rev 6

Embedded Flash memory (FLASH)

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