ST STM32L4+ Series Reference Manual page 595

RM0432
19.6.15 OCTOSPI timing configuration register (OCTOSPI_TCR)
Address offset: 0x0108
Reset value: 0x0000 0000
31 30 29 28
SSHIF
Res. Res. DHQC
T
rw rw
15 14 13 12
Res. Res. Res. Res.
Bit 31 Reserved, must be kept at reset value.
Bit 30 SSHIFT: Sample shift
By default, the OCTOSPI samples data 1/2 of a CLK cycle after the data is driven by the
external device.
This bit allows the data to be sampled later in order to consider the external signal delays.
0: No shift
1: 1/2 cycle shift
The software must ensure that SSHIFT = 0 when the data phase is configured in DTR mode
(when DDTR = 1.)
This field can be modified only when BUSY = 0.
Bit 29 Reserved, must be kept at reset value.
Bit 28 DHQC: Delay hold quarter cycle
0: No delay hold
1: 1/4 cycle hold
Bits 27:5 Reserved, must be kept at reset value.
Bits 4:0 DCYC[4:0]: Number of dummy cycles
This field defines the duration of the dummy phase.
In both SDR and DTR modes, it specifies a number of CLK cycles (0-31).
It is recommended to have at least six dummy cycles when using memories with DQS
activated.
This field can be written only when BUSY = 0.
19.6.16 OCTOSPI instruction register (OCTOSPI_IR)
Address offset: 0x0110
Reset value: 0x0000 0000
31 30 29 28
rw rw rw rw
15 14 13 12
rw rw rw rw
27 26 25 24
Res. Res. Res. Res.
11 10 9 8
Res. Res. Res. Res.
27 26 25 24
INSTRUCTION[31:16]
rw rw rw rw
11 10 9 8
INSTRUCTION[15:0]
rw rw rw rw
RM0432 Rev 6
Octo-SPI interface (OCTOSPI)
23 22 21 20
Res. Res. Res. Res.
7 6 5 4
Res. Res. Res.
rw
23 22 21 20
rw rw rw rw
7 6 5 4
rw rw rw rw
19 18 17 16
Res. Res. Res. Res.
3 2 1 0
DCYC[4:0]
rw rw rw rw
19 18 17 16
rw rw rw rw
3 2 1 0
rw rw rw rw
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