ST STM32L4+ Series Reference Manual page 730

Digital-to-analog converter (DAC)
22.4.4 DAC conversion
The DAC_DORx cannot be written directly and any data transfer to the DAC channelx must
be performed by loading the DAC_DHRx register (write operation to DAC_DHR8Rx,
DAC_DHR12Lx, DAC_DHR12Rx, DAC_DHR8RD, DAC_DHR12RD or DAC_DHR12LD).
Data stored in the DAC_DHRx register are automatically transferred to the DAC_DORx
register after one APB1 clock cycle, if no hardware trigger is selected (TENx bit in DAC_CR
register is reset). However, when a hardware trigger is selected (TENx bit in DAC_CR
register is set) and a trigger occurs, the transfer is performed three APB1 clock cycles after
the trigger signal.
When DAC_DORx is loaded with the DAC_DHRx contents, the analog output voltage
becomes available after a time t
analog output load.
HFSEL bit of DAC_CR must be set when APB1 clock speed is faster than 80 MHz. It adds
an extra delay of three APB1 clock cycles to the transfer from DAC_DHRx register to
DAC_DORx register (t
The DAC_DORx update rate is limited to 1/3 of APB1 clock frequency. When HFSEL bit is
set, this rate is limited to 1/8 of the APB1 clock frequency.
When HFSEL is set, it is not allowed to write the DHRx register during a period of eight clock
cycles after the ENx bit is set. During this period, making software/hardware triggering is not
allowed either.
Figure 161. Timing diagram for conversion with trigger disabled TEN = 0
APB1_CLK
22.4.5 DAC output voltage
Digital inputs are converted to output voltages on a linear conversion between 0 and V
The analog output voltages on each DAC channel pin are determined by the following
equation:
DACoutput
730/2301
SETTLING
DHR
DOR
DOR
------------- -
V ×
=
REF
4096
that depends on the power supply voltage and the
SETTLING
).
0x1AC
0x1AC
t
SETTLING
RM0432 Rev 6
RM0432
Output voltage
available on DAC_OUT pin
ai14711c
REF+
.