ST STM32L4+ Series Reference Manual page 983

RM0432
30.14.9 Managing ULPM
There are two ways to configure the software to enter and exit the ULPM:
•
Enter and Exit the ULPM with the D-PHY PLL running. This is a faster process.
•
Enter and Exit the ULPM with the D-PHY PLL turned off. This is a more efficient
process in terms of power consumption.
Clock management for ULPM sequence
The ULPM management state machine is working on the lanebyteclock provided by the D-
PHY.
Because the D-PHY is providing the lanebyteclock only when the clock lane is not in ULPM
state, it is mandatory to switch the lanebyteclock source of the DSI Host before starting the
ULPM mode entry sequence.
The lanebyteclock source is controlled by the RCC. It can be
•
the lanebyteclock provided by the D-PHY (for all modes except ULPM)
•
a clock generated by the system PLL (for ULPM)
Process flow to enter the ULPM
Implement the process described in detail in the following procedure to enter the ULPM on
both clock lane and data lanes:
1. Verify the initial status of the DSI Host:
–
–
–
–
–
2. Switch the lanebyteclock source in the RCC from D-PHY to system PLL
3. Set DSI_PUCR[3:0] = 4'h5 to enter ULPM in the data and the clock lanes.
4. Wait until the D-PHY active lanes enter into ULPM:
–
–
The DSI Host is now in ULPM.
5. Turn off the D-PHY PLL by setting DSI_WRPCR.PLLEN = 1'b0
DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only
DSI_PCTLR[2:1] = 2'h3
DSI_WRPCR.PLLEN = 1'h1 & DSI_WRPCR.REGEN = 1'h1
DSI_PUCR[3:0] = 4'h0
DSI_PTTCR[3:0] = 4'h0
Verify that all active lanes are in Stop state and the D-PHY PLL is locked:
One-lane configuration: DSI_PSR[6:4] = 3'h3 & DSI_PSR[1] = 1'h0 &
DSI_WISR.PLLS = 1'h1
Two -lanes configuration: DSI_PSR[8:4] = 5'h1B & DSI_PSR[1] = 1'h0 &
DSI__WISR.PLLS = 1'h1
One-lane configuration: DSI_PSR[6:1] = 6'h00
Two-lanes configuration: DSI_PSR[8:1] = 8'h00
RM0432 Rev 6 983/2301
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