ST STM32L4+ Series Reference Manual page 1000

DSI Host (DSIHOST) applied to STM32L4R9xx and STM32L4S9xx only
30.15.26 DSI Host Generic Packet Status Register (DSI_GPSR)
Address offset: 0x0074
Reset value: 0x0000 0015
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31: 7 Reserved, must be kept at reset value
Bit 6 RCB: Read Command Busy
Bit 5 PRDFF: Payload Read FIFO Full
Bit 4 PRDFE: Payload Read FIFO Empty
Bit 3 PWRFF: Payload Write FIFO Full
Bit 2 PWRFE: Payload Write FIFO Empty
Bit 1 CMDFF: Command FIFO Full
Bit 0 CMDFE: Command FIFO Empty
1000/2301
27 26 25
Res. Res. Res.
11 10 9
Res. Res. Res.
This bit is set when a read command is issued and cleared when the entire response is
stored in the FIFO:
0: No read command on going.
1: Read command on going.
This bit indicates the full status of the generic read payload FIFO:
0: Read payload FIFO not full.
1: Read payload FIFO full.
This bit indicates the empty status of the generic read payload FIFO:
0: Read payload FIFO not empty.
1: Read payload FIFO empty.
This bit indicates the full status of the generic write payload FIFO:
0: Write payload FIFO not full.
1: Write payload FIFO full.
This bit indicates the empty status of the generic write payload FIFO:
0: Write payload FIFO not empty.
1: Write payload FIFO empty.
This bit indicates the full status of the generic command FIFO:
0: Write payload FIFO not full.
1: Write payload FIFO full.
This bit indicates the empty status of the generic command FIFO:
0: Write payload FIFO not empty.
1: Write payload FIFO empty.
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
Res. Res. RCB PRDFF
ro ro
RM0432 Rev 6
20 19 18
Res. Res. Res.
4 3 2
PRDFE PWRFF PWRFE CMDFF CMDFE
ro ro ro
RM0432
17 16
Res. Res.
1 0
ro ro