ST STM32L4+ Series Reference Manual page 892

LCD-TFT display controller (LTDC)
The LTDC-TFT controller pins must be configured by the user application. The unused pins
can be used for other purposes.
For LTDC outputs up to 24 bits (RGB888), if less than 8 bpp are used to output for example
RGB565 or RGB666 to interface on 16- or 18-bit displays, the RGB display data lines must
be connected to the MSB of the LCD-TFT controller RGB data lines. As an example, in the
case of an LCD-TFT controller interfacing with a RGB565 16-bit display, the LCD display
R[4:0], G[5:0] and B[4:0] data lines pins must be connected to LCD-TFT controller
LCD_R[7:3], LCD_G[7:2] and LCD_B[7:3].
29.4.3 LTDC reset and clocks
The LCD-TFT controller peripheral uses the following clock domains:
•
AHB clock domain (HCLK)
This domain contains the LCD-TFT AHB master interface for data transfer from the
memories to the Layer FIFO and the frame buffer configuration register
• APB2 clock domain (PCLK2):
This domain contains the global configuration registers and the interrupt register.
• Pixel clock domain (LCD_CLK)
This domain contains the pixel data generation, the layer configuration register as well
as the LCD-TFT interface signal generator. The LCD_CLK output should be configured
following the panel requirements. The LCD_CLK is generated from a specific PLL
output (refer to the reset and clock control section).
The table below summarizes the clock domain for each register.
LTDC_LxCR
LTDC_LxCFBAR
LTDC_LxCFBLR
LTDC_LxCFBLNR
LTDC_SRCR
LTDC_IER
LTDC_ISR
LTDC_ICR
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Table 194. Clock domain for each register
LTDC register
RM0432 Rev 6
Clock domain
HCLK
PCLK2
RM0432